The present disclosure relates to semiconductor devices, and in particular to an integrated circuit assembly having a cushion polymer layer.
Integrated circuits are typically formed by forming semiconductor circuitry on a silicon substrate. During the manufacturing process, a handle layer may be attached to the semiconductor circuitry via an adhesive. In some circuits, through-silicon vias (TVs) are formed in the silicon substrate to connect the semiconductor circuitry on one side of the silicon substrate with electrical connectors on the opposite side of the silicon substrate. An insulator layer is typically formed around the conductor of the TSVs and on the back side of the silicon substrate to prevent diffusion of metals into the silicon substrate.
During manufacturing, and testing, the integrated circuit device is subjected to stresses, including physical stresses caused by physically and electrically connecting contacts on the back side of the silicon substrate to other devices, by planarizing or polishing the back side of the silicon substrate, or by other processes. These stresses may cause flaws to appear in one or more of the TSVs, the dielectric layer around the TSVs, the dielectric layer formed on the back side of the silicon substrate, and the metal contacts that connect the TSVs to other devices. These flaws may result in electrical failures of the integrated circuit device.